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general description the max125/MAX126 are high-speed, multichannel, 14-bit data-acquisition systems (das) with simultaneous track/holds (t/hs). these devices contain a 14-bit, 3?, successive-approximation analog-to-digital converter (adc), a +2.5v reference, a buffered reference input, and a bank of four simultaneous-sampling t/h ampli- fiers that preserve the relative phase information of the sampled inputs. the max125/MAX126 have two multi- plexed inputs for each t/h, allowing a total of eight inputs. in addition, the converter is overvoltage tolerant to ?7v; a fault condition on any channel will not harm the ic. available input ranges are ?v (max125) and ?.5v (MAX126). an on-board sequencer converts one to four channels per convst pulse. in the default mode, one t/h output (ch1a) is converted. an interrupt signal ( int ) is provided after the last conversion is complete. convert two, three, or four channels by reprogramming the max125/MAX126 through the bidirectional parallel interface. once programmed, the max125/MAX126 continue to convert the specified number of channels per convst pulse until they are reprogrammed. the channels are converted sequentially, beginning with ch1. the int signal always follows the end of the last conversion in a conversion sequence. the adc con- verts each assigned channel in 3? and stores the result in an internal 14x4 ram. upon completion of the conversions, data can be accessed by applying suc- cessive pulses to the rd pin. four successive reads access four data words sequentially. the parallel interface? data-access and bus-release timing specifications are compatible with most popular digital signal processors and 16-bit/32-bit microproces- sors, so the max125/MAX126 conversion results can be accessed without resorting to wait states. applications multiphase motor control power-grid synchronization power-factor monitoring digital signal processing vibration and waveform analysis features four simultaneous-sampling t/h amplifiers with two multiplexed inputs (eight single-ended inputs total) 3? conversion time per channel throughput: 250ksps (1 channel) 142ksps (2 channels) 100ksps (3 channels) 76ksps (4 channels) input range: ?v (max125) ?.5v (MAX126) fault-protected input multiplexer (?7v) ?v supplies internal +2.5v or external reference operation programmable on-board sequencer high-speed parallel dsp interface max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das ________________________________________________________________ maxim integrated products 1 ordering information 19-1319; rev 2; 6/07 for pricing delivery, and ordering information please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. typical operating circuit appears at end of data sheet. pin configuration appears at end of data sheet. evaluation kit available part temp range pin- package inl (lsb) pkg code max125 ccax 0? to +70? 36 ssop ? a36-4 max125ceax -40? to +85? 36 ssop ? a36-4 MAX126 ccax 0? to +70? 36 ssop ? a36-4 MAX126ceax -40? to +85? 36 ssop ? a36-4
max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = +5v ?%, av ss = -5v ?%, dv dd = +5v ?%, v refin = 2.5v, agnd = dgnd = 0v, 4.7? capacitor from refout to agnd, 0.1? capacitor from refin to agnd, f clk = 16mhz, external clock, 50% duty cycle, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd ...........................................................-0.3v to 6v av ss to agnd ............................................................0.3v to -6v dv dd to dgnd ...........................................................-0.3v to 6v agnd to dgnd .......................................................-0.3v to 0.3v ch_ _ to agnd....................................................................?7v refin, refout to agnd ..........................................-0.3v to 6v digital inputs/outputs to dgnd ..............-0.3v to (dv dd + 0.3v) continuous power dissipation (t a = +70?) ssop (derate 11.8mw/? above +70?) ....................941mw operating temperature ranges max125ccax/MAX126ccax ............................0? to +70? max125ceax/MAX126ceax ..........................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10sec)................................300? parameter symbol conditions min typ max units dc accuracy (note 1) resolution n all channels 14 bits integral nonlinearity inl (note 2) ? ? lsb differential nonlinearity dnl guaranteed monotonic to 13 bits ? lsb t a = +25? 5 ?5 bipolar zero error t a = t min to t max ?5 mv bipolar zero-error match between all channels 1.2 5 mv zero-code tempco ? ppm/? t a = +25? 5 ?0 gain error t a = t min to t max ?5 mv gain-error match between all channels 1.2 5 mv gain-error tempco ? ppm/? dynamic performance (f clk = 16mhz, f in = 10.06khz (notes 1, 3) max125 72 75 signal-to-noise plus distortion sinad single-channel mode, channel 1a, 250ksps (note 4) MAX126 70 72 db total harmonic distortion thd single-channel mode, channel 1a, 250ksps (notes 4, 5) -89 -80 db spurious-free dynamic range sfdr single-channel mode, channel 1a, 250ksps (note 4) 80 90 db channel-to-channel isolation single-channel mode, channel 1a, 250ksps (note 6) 80 db
a max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = +5v 5%, av ss = -5v 5%, dv dd = +5v 5%, v refin = 2.5v, agnd = dgnd = 0v, 4.7 f capacitor from refout to agnd, 0.1 f capacitor from refin to agnd, f clk = 16mhz, external clock, 50% duty cycle, t a = t min to t max , unless otherwise noted.) conditions units min typ max symbol parameter max125 v 5 v in input voltage range max125, v in = 5v a 667 i in input current (note 7) pf 16 c in input capacitance s 1 t acq acquisition time mhz 8 small-signal bandwidth mhz 0.5 full-power bandwidth mv/ms 2 droop rate ns 5 aperture delay ps rms 30 aperture jitter ps 500 aperture-delay matching t a = +25 c v 2.475 2.500 2.525 v refout output voltage 0ma < i load < 1ma % 1 external load regulation (note 9) ppm/ c 30 refout tempco f 0.1 external capacitive bypass at refin v 2.50 10% input voltage range f 4.7 22 external capacitive bypass at refout refin = 2.5v a 10 input current (note 10) k 10 input resistance (note 7) pf 10 input capacitance mhz 0.1 16 external clock frequency v 2.4 v ih input high voltage v 0.8 v il input low voltage convst, rd , wr , cs , clk 1 (note 7) pf 15 c in input capacitance a0?3 a 10 i in input current MAX126 2.5 MAX126, v in = 2.5v analog input track/hold reference output (note 8) reference input external clock digital inputs ( convst , rd, wr , cs , clk, a0?3) (note 1)
max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das 4 _______________________________________________________________________________________ conditions units min typ max symbol parameter i out = 1ma v 4 v oh output high voltage i out = -1.6ma v 0.4 v ol output low voltage d0?13 a 10 three-state leakage current (note 7) pf 10 three-state output capacitance v 4.75 5 5.25 av dd positive supply voltage v -5.25 -5 -4.75 av ss negative supply voltage v 4.75 5 5.25 dv dd digital supply voltage ma 17 25 i(av dd ) positive supply current ma -17 -13 i(av ss ) negative supply current ma 3 5 i(dv dd ) digital supply current ma 3 shutdown positive current ma -1 shutdown negative current ma 3 shutdown digital current (note 11) lsb 1 2 psrr+ positive supply rejection (note 11) lsb 2 psrr- negative supply rejection (note 12) mw 165 250 power dissipation digital outputs (d0?13, int ) (note 1) power requirements electrical characteristics (continued) (av dd = +5v 5%, av ss = -5v 5%, dv dd = +5v 5%, v refin = 2.5v, agnd = dgnd = 0v, 4.7 f capacitor from refout to agnd, 0.1 f capacitor from refin to agnd, f clk = 16mhz, external clock, 50% duty cycle, t a = t min to t max , unless otherwise noted.)
max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das _______________________________________________________________________________________ 5 conditions ns 30 t cw convst pulse width units min typ max symbol parameter timing characteristics (figure 4) (av dd = +5v, av ss = -5v, dv dd = +5v, agnd = dgnd = 0v, t a = t min to t max , unless otherwise noted.) ns 0 t cws cs to wr setup time ns 0 t cwh cs to wr hold time ns 30 t wr wr low pulse width ns 125 t csd cs to convst delay ns 30 t as address setup time ns 0 t ah address hold time 25pf load ns 30 t id rd to int delay ns 40 t rd delay time between reads ns 0 t crs cs to rd setup time ns 0 t crh cs to rd hold time ns 30 t rd rd low pulse width 25pf load (note 13) ns 30 t da data-access time 25pf load (note 14) ns 5 45 t dh bus-relinquish time mode 1, 1 channel s 3 mode 2, 2 channel 6 mode 3, 3 channel 9 mode 4, 4 channel 12 t conv exiting shutdown s 5 start-up time note 1: av dd = +5v, av ss = -5v, dv dd = +5v, v refin = 2.500v (external), v in = 5v (max125) or 2.5v (MAX126). note 2: relative accuracy is the analog value? deviation at any code from its theoretical value after the full-scale range has been calibrated. note 3: clk synchronized with convst . note 4: f in = 10.06khz, v in = 5v (max125) or 2.5v (MAX126). note 5: first five harmonics. note 6: all inputs except ch1a driven with 5v (max125) or 2.5v (MAX126) 10khz signal; ch1a connected to agnd and digitized . note 7: guaranteed by design. not production tested. note 8: av dd = +5v, av ss = -5v, dv dd = +5v, v in = 0v (all channels). note 9: temperature drift is defined as the change in output voltage from +25 c to t min or t max . it is calculated as tc = [ ? refout/refout] / ? t. note 10: see figure 2. note 11: defined as the change in positive full scale caused by a 5% variation in the nominal supply voltage. tested with one input at full scale and all others at agnd. v refin = 2.5v (internal). note 12: tested with v in = agnd on all channels, v refin = 2.5v (internal). note 13: the data-access time is defined as the time required for an output to cross 0.8v or 2.0v. it is measured using the circuit of figure 1. the measured number is then extrapolated back to determine the value with a 25pf load. note 14: the bus-relinquish time is derived from the measured time taken for the data outputs to change 0.5v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging/discharging the 120pf capacitor. thus, the time given is the part? true bus-relinquish time, independent of the external bus loading capacitance. conversion time mode 1, 1 channel ksps 250 conversion rate/channel mode 2, 2 channel 142 mode 3, 3 channel 100 mode 4, 4 channel 76
_______________ detailed description the max125/MAX126 use a successive-approximation conversion technique and four simultaneous-sampling track/hold (t/h) amplifiers to convert analog signals into 14-bit digital outputs. each t/h has two multiplexed inputs, allowing a total of eight inputs. each t/h output is converted and stored in memory to be accessed sequentially by the parallel interface with successive read cycles. the max125/MAX126 internal micro- sequencer can be programmed to digitize one, two, three, or four inputs sampled simultaneously from either of the two banks of four inputs (see figure 2). the conversion timing and control sequences are derived from a 16mhz external clock, the convst max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das 6 _______________________________________________________________________________________ name function 1, 2 ch2b, ch2a channel 2 multiplexed inputs, single-ended 3, 4 ch1b, ch1a channel 1 multiplexed inputs, single-ended pin 5 av dd +5v 5% analog supply voltage 6 refin external reference input/internal reference output. bypass with a 0.1 f capacitor to agnd. 17 dv dd +5v 5% digital supply voltage 9 16 d13?6 data bits. d13 = msb. 8, 36 agnd analog ground. both pins must be tied to ground. 7 refout reference-buffer output. bypass with a 4.7 f capacitor to agnd. 26 cs chip-select input (active-low) 25 clk clock input (duty cycle must be 30% to 70%). 21?4 d3/a3?0/a0 bidirectional data bits/address bits. d0/a0 = lsb. 19, 20 d5, d4 data bits 18 dgnd digital ground ______________________________________________________________ pin description 27 wr write input (active-low) 28 rd read input (active-low) 29 convst conversion-start input. rising edge initiates sampling and conversion sequence. 30 int interrupt output. falling edge indicates the end of a conversion sequence. 31 av ss -5v 5% analog supply voltage 32, 33 ch4a, ch4b channel 4 multiplexed inputs, single-ended 34, 35 ch3a, ch3b channel 3 multiplexed inputs, single-ended figure 1. load circuit for access time and bus relinquish time to output pin 120pf 1.0ma 1.6ma 1.6v
max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das _______________________________________________________________________________________ 7 mux 2.50v bandgap reference refin 10k agnd refout mux t/h t/h t/h t/h a b mux a b mux a b mux ch1a ch1b ch2a ch2b ch3a ch3b ch4a ch4b a b 14-bit dac control logic bus interface clk convst int cs rd wr dv dd dgnd sar 14x4 ram v ref three-state output drivers av dd agnd av ss d0/a0 (lsb) d1/a1 d2/a2 d3/a3 d13 (msb) max125 MAX126 v ref comp figure 2. functional diagram
max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das 8 _______________________________________________________________________________________ signal, and the programmed mode. the t/h amplifiers hold the input voltages at the convst rising edge. additional convst pulses are ignored until the last conversion for the sample is complete. the adc con - verts each assigned channel in 3 s and stores the result in an internal 4x14-bit memory. at the end of the last conversion, int goes low and the t/h amplifiers begin to track the inputs again. the data can be accessed by applying successive pulses to the rd pin. successive reads access data words sequen - tially. the memory is not random-access; data from ch1 is always read first. after accessing all pro - grammed channels, the address pointer selects ch1 again. additional read pulses cycle through the data words. cs can be held low during successive reads. input bandwidth the t/h? input tracking circuitry has an 8mhz small- signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high- frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog input range and input protection the max125? input range is 5v, and the MAX126? input range is 2.5v. the input resistance for both parts is 10k . an input protection structure allows input volt - ages to 17v without harming the ic. this protection is also active in shutdown mode. track/holds the max125/MAX126 feature four simultaneous t/hs. each t/h has two multiplexed inputs. a t-switch input configuration provides excellent hold-mode isolation. allow 1 s acquisition time for 14-bit accuracy. the t/h aperture delay is typically 10ns. the 500ps aperture-delay mismatch between the t/hs allows the relative phase information of up to four different inputs to be preserved. figure 3 shows the equivalent input circuit, illustrating the adc? sampling architecture. only one of four t/h stages with its two multiplexed inputs (ch_a and ch_b) is shown. all switches are in track configuration for channel a. an internal buffer charges the hold capacitor to minimize the required acquisition time between conversions. the analog input appears as a 10k resistor in parallel with a 16pf capacitor. c in 5k c in 5k s1a s2a hold buffer track c hold 7pf hold from microsequencer refout track mux dac sar s1b s2b s3b s3a 5k 5k ch_a ch_b max125 MAX126 figure 3. equivalent input circuit
between conversions, the buffer input is connected to channel 1 of the selected track/hold bank. when a channel is not selected, switches s1, s2, and s3 are placed in hold mode to improve channel-to-channel isolation. digital interface input data (a0?3) and output data (d0?13) are multi - plexed on a three-state bidirectional interface. this par - allel i/o can easily be interfaced with a microprocessor ( p) or dsp. cs , wr , and rd control the write and read operations. cs is the standard chip-select signal, which enables the controller to address the max125/MAX126 as an i/o port. when cs is high, it disables the wr and rd inputs and forces the interface into a high-z state. figure 4 details the interface timing. programming modes t he max125/MAX126 have eight conversion modes plus power-down, which are programmed through a bidirectional parallel interface. at power-up, the devices default to the mode input mux a/single-channel conversion. the user can select between two banks (mux inputs a or mux inputs b) of four simultaneous- sampled input channels, as illustrated in figure 2. an internal microsequencer can be programmed to convert one, two, three, or four channels of the selected bank per sample. for a single-channel conversion, ch1 is digitized, and then int goes low to indicate completion of the conversion. for multichannel conversions, int goes low after the last channel has been digitized. to input data into the max125/MAX126, pull cs low, program the bidirectional pins a0?3 (table 1), and pulse wr low. data is latched into the devices on the wr or cs rising edge. the adc is now ready to convert. once programmed, the adcs continue operating in the same mode until they are reprogrammed or until power is removed. figure 5 shows an example of program - ming a four-channel conversion using input mux a. starting a conversion after programming the max125/MAX126 as outlined in the programming modes section, pulse convst low to initiate a conversion sequence. the analog inputs are sampled at the convst rising edge. do not start a new conversion while the conversion is in progress. monitor the int output. a falling edge indicates the end of a conversion sequence. max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das _______________________________________________________________________________________ 9 ch1 ch2 ch3 ch4 t acq t conv t ah t as t wr t csd t cwh t dh t da t rd t crs t crh t rd t id t cws convst int cs wr data t cw data in rd figure 4. timing diagram figure 5. programming a four-channel conversion, input mux a a0 (lsb) wr cs a1 a2 a3
max125/MAX126 reading a conversion digitized data from up to four channels are stored in memory to be read out through the parallel interface. after receiving an i nt signal, the user can access up to four conversion results by performing up to four read operations. with cs low, the conversion result from ch_1 is accessed, and int is reset high on the first rd falling edge. on the rd rising edge, the internal address pointer is advanced. if a single conversion is pro - grammed, only one rd pulse is required, and the address pointer is reset to ch_1. for multichannel con - versions, up to four rd falling edges sequentially access the data for channels 1 through 4. for n chan - nels converted (1 < n 4), the address pointer is reset to ch_1 after n rd pulses. do not perform a read oper - ation during conversion, as it will corrupt the conver - sion? accuracy. __________ applications infor mation external clock the max125/MAX126 require a ttl-compatible clock up to 16mhz for proper operation. the clock duty cycle? range is between 30% and 70%. internal and external reference the max125/MAX126 can be used with an internal or external reference voltage. an external reference can be connected directly at refin. an internal buffer with a gain of +1 provides 2.5v at refout. internal reference the full-scale range with the internal reference is 5v for the max125 and 2.5v for the MAX126. bypass refin with a 0.1 f capacitor to agnd and bypass the refout pin with a 4.7 f (min) capacitor to agnd (figure 6). the maximum value to compensate the ref - erence buffer is 22 f. larger values are acceptable if low-esr capacitors are used. external reference for operation over a wide temperature range, an exter - nal 2.5v reference with tighter specifications improves accuracy. the max6325 is an excellent choice to match the max125/MAX126 accuracy over the commercial and extended temperature ranges with a 2x4-channel, simultaneous-sampling 14-bit das 10 ______________________________________________________________________________________ x = don? care table 1. modes of operation a3 a2 a1 0 0 0 0 0 0 0 0 1 0 0 1 a0 0 1 0 1 conversion time ( s) 3 6 9 12 mode input mux a/two-channel conversion input mux a/three-channel conversion input mux a/four-channel conversion 0 1 0 0 3 input mux b/single-channel conversion 0 1 0 1 6 input mux b/two-channel conversion 0 1 1 0 9 input mux b/three-channel conversion 0 1 1 1 12 input mux b/four-channel conversion 1 x x x power-down to dac refin 10k 0.1 m f 4.7 m f a v = 1 2.5v refout 7 6 (2.5v) (2.5v) max125 MAX126 figure 6. internal reference input mux a/single-channel conversion (default at power-up)
1ppm/ c (max) temperature drift. connect an external reference at refin as shown in figure 7. the minimum impedance is 7k for dc currents in both normal oper - ation and shutdown. bypass refout with a 4.7 f low- esr capacitor. power-on reset when power is first applied, the internal power-on-reset circuitry activates the max125/MAX126 with int = high, ready to convert. the default conversion mode is input mux a/single-channel conversion. see the programming modes section if other configurations are desired. after the power supplies have been stabilized, the reset time is 5 s; no conversions should be performed during this phase. at power-up, data in memory is undefined. software power-down software power-down is activated by setting bit a3 of the control word high (table 1). it is asserted after the wr or cs rising edge, at which point the adc immedi - ately powers down to a low quiescent-current state. av dd drops to less than 1.5ma, and av ss is reduced to less than 1ma. the adc blocks and reference buffer are turned off, but the digital interface and the refer - ence remain active for fast power-up recovery. wake up the max125/MAX126 by writing a control word (a0?3, table 1). the bidirectional interface interprets a logic zero at a3 as the start signal and powers up in the mode selected by a0, a1, and a2. the reference buffer? settling time and the bypass capacitor? value dominate the power-up delay. with the recommended 4.7 f at refout, the power-up delay is typically 5 s. transfer function the max125/MAX126 have bipolar input ranges. fig- ure 8 shows the bipolar/output transfer function. code transitions occur at successive-integer least significant bit (lsb) values. output coding is twos-complement binary with 1lsb = 610 v for the max125 and 1lsb = 305 v for the MAX126. output demultiplexer an output demultiplexer circuit is useful for isolating data from one channel in a four-channel conversion sequence. figure 9? circuit uses the external 16mhz clock and the int signal to generate four rd pulses and a latch clock to save data from the desired chan - nel. cs must be low during the four rd pulses. the channel is selected with the binary coding of two switches. a 16-bit 16373 latch simplifies layout. motor-control applications vector motor control requires monitoring of the individ - ual phase currents. in their most basic application, the max125/MAX126 simultaneously sample two currents (ch1a and ch2a, figure 10) and preserve the neces - sary relative phase information. only two of the three phase currents have to be digitized, because the third component can be mathematically derived with a coor - dinate transformation. max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das ______________________________________________________________________________________ 11 to dac refin 10k 4.7 m f a v = 1 2.5v refout 7 6 (2.5v) (2.5v) out max6325 max125 MAX126 figure 7. external reference 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs zero input voltage (lsb) fs = 2 x v refout (max125) fs = v refout (MAX126) output code +fs - 1lsb 1lsb = 4v refout 16384 figure 8. bipolar transfer function
max125/MAX126 the circuit of figure 10 shows a typical vector motor- control application using all available inputs of the max125/MAX126. ch1a and ch2a are connected to two isolated hall-effect current sensors and are a part of the current (torque) feedback loop. the max125/MAX126 digitize the currents and deliver raw data to the following dsp and controller stages, where the vector processing takes place. sensorless vector control uses a computer model for the motor and an algorithm to split each output current into its magnetiz - ing (stator current) and torque-producing (rotor current) components. if a 2- to 3-phase conversion is not practical, three cur - rents can be sampled simultaneously with the addition of a third sensor (not shown). optional voltage (position) feedback can be derived by measuring two phase voltages (ch3a, ch4a). typically, an isolated differential amplifier is used between the motor and the max125/MAX126. again, the third phase voltage can be derived from the magnitude (phase voltage) and its relative phase. for optimum speed control and good load regulation close to zero speed, additional velocity and position feedback are derived from an encoder or resolver and 2x4-channel, simultaneous-sampling 14-bit das 12 ______________________________________________________________________________________ pre clr hc161 1/2 hc74 v cc v cc v cc enp ent load a b c d (lsb) 0 1 2 3 rco d q q clr p0 p1 p2 p3 p4 p5 p6 p7 hc688 p = q q0 q1 q2 v cc q3 q4 q5 q6 q7 g latch clock (to 16373 latch) 0 ch1 0 1 ch2 0 0 ch3 1 1 ch4 1 10k external clock external clock rd int figure 9. output demultiplexer circuit
max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das ______________________________________________________________________________________ 13 figure 10. vector motor control brought to the max125/MAX126 at ch4b. the addi - tional channels can be used to evaluate slower analog inputs, such as the main dc bus voltage (ch2b), tem - perature sensors (ch3b), or other analog inputs (aux, ch1b). power-supply bypassing and ground management for optimum system performance, use printed circuit boards with separate analog and digital ground planes. wire-wrapped boards are not recommended. connect the two ground planes together at the low- impedance power-supply source. connect dgnd and agnd together at the ic. for the best ground connec - tion, connect the dgnd and agnd pins together and connect that point to the system analog ground plane to avoid interference from other digital noise sources. if dgnd is connected to the system digital ground, digi - tal noise may get through to the adc? analog portion. the agnd pins must be connected directly to a low- impedance ground plane. extra impedance between the pins and the ground plane increases crosstalk and degrades inl. bypass av dd and av ss with 0.1 f ceramic capacitors to agnd. mount them with short leads close to the device. ferrite beads may also be used to further iso - late the analog and digital power supplies. bypass dv dd with a 0.1 f ceramic capacitor to dgnd. main dc 14 bit adc + micro- sequencer ch1 ch2 ch3 ch4 a b a b temp a b a b aux main dc current/torque feedback voltage/position feedback velocity feedback ac motor simultaneous t/h max125 MAX126 ac motor r/e resolver/ encoder m c dsp 14 buffer power stage controller external setpoints
max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das 14 ______________________________________________________________________________________ 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 agnd ch3b ch3a ch4b ch4a av ss d1/a1 int convst rd wr cs clk d0/a0 (lsb) d8 d9 d10 d11 d12 d13 (msb) agnd refout refin av dd ch1a ch1b ch2a ch2b ssop top view max125 MAX126 22 21 20 19 15 16 17 18 d5 d2/a2 d3/a3 d4 dgnd dv dd d6 d7 __________________ pin configuration d0/a0 d1/a1 d2/a2 d3/a3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 ch1a ch1b ch2a ch2b ch3a ch3b ch4a ch4b max125 MAX126 convst control interface clk refout dgnd agnd refin dv dd 4.7 m f 16mhz 0.1 m f 0.1 m f -5v 0.1 m f +5v 0.1 m f +5v av ss av dd int cs rd wr __________ t ypical operating cir cuit transistor count: 4219 substrate connected to av ss ___________________ chip infor mation
max125/MAX126 2x4-channel, simultaneous-sampling 14-bit das maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history pages changed at rev 2: 1, 2, 15 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) ssop.eps package outline, 36l ssop, 0.80 mm pitch 1 1 21-0040 e rev. document control no. approval proprietary information title: front view max 0.011 0.104 0.017 0.299 0.013 inches 0.291 0.009 e c dim 0.012 0.004 b a1 min 0.096 a 0.23 7.40 7.60 0.32 millimeters 0.10 0.30 2.44 min 0.44 0.29 max 2.65 0.040 0.020 l 0.51 1.02 h 0.414 0.398 10.11 10.51 e 0.0315 bsc 0.80 bsc d 0.612 0.598 15.20 15.55 h e a1 a d e b 0 -8 l c top view side view 1 36

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